1. Field of the Invention
The present invention in general relates to a shift register and a driver circuit of liquid crystal display adopting the shift register, and more particularly, to a shift register that adopts a shift delay for each memory device, or a data conversion control system through the estimation of conversion of data storage state. The present invention further relates to a driver circuit of LCD adopting such a shift register, which can prevent instantaneous increase of electric power consumption as well as EMI (electromagnetic interference) occurrence.
2. Description of the Related Art
A shift register is a logic circuit having memory devices such as flip flop or latch arranged in line so as to sequentially shift input data between memory devices and stores predetermined amount of data.
Typically, shift registers have been widely used in a digital circuitry for processing digital data in a variety of fields. Specifically, shift registers are employed for timing controllers and driver ICs to drive an LCD that has been widely used as a flat panel display device. In such a case, a shift register is used for generating a control signal or delaying data for a predetermined time period.
A conventional shift register is configured such that data stored in the entire register can be simultaneously shifted in a direction at a rising time of clock, and data input/output is determined in accordance with a first-in first-out principle.
In detail, as for the shift register for processing 4-bit data, data D0, D1, D2, D3 are shifted for each of memory devices sequentially from the data input initially and move in a direction, and such data shift is synchronized with a clock. In addition, outputs D0, D1, D2 and D3 are output in the same order as they are input.
To perform such an operation, a large amount of current is required to be supplied to a logic circuit instantaneously for driving a shift register since the shift register is synchronized with clocks during such an operation and each of memory devices operates at the same time. This consumes a large amount of power instantaneously while producing EMI.
This phenomenon is fortified when the data stored in the shift register change the state significantly. More specifically, a large amount of electric power is required when a memory device changes logic 0 or logic 1 so as to perform shift operation synchronized with a clock signal. The increased number of shift registers requiring the state change requires low power consumption and decreased EMI.